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Annex 1 (BE01) — Lesson BE.01.08 • TLO: 28XX-MAIN-1002 • ELOs: 28XX-MAIN-1002ba, 1002be, 1002bh, 1002bl

Series-Parallel Resistive Circuits

A series-parallel (combination) circuit combines series elements and parallel banks within the same network. To the DC power supply, the entire combination network still appears as a single total resistance (RTR_T). Solving or troubleshooting any series-parallel circuit requires applying series rules to the series sections and parallel rules to the parallel sections in a strict six-step order of operations.


1. The Mandatory 6-Step Reduction & Solution Process

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VA R1 (Series) R2 R3 (RL) 1. Original Circuit (R1 + [R2 ∥ R3]) Step 1–2 VA R1 REQ 2. Redrawn Series Circuit (RT = R1 + REQ)

Step-by-Step Order of Operations (ELO 28XX-MAIN-1002ba)

Step Action Governing Rule & Formula
Step 1 Work Out All Parallel Sections (REQR_{EQ}) Reduce every parallel bank to a single Equivalent Resistance (REQR_{EQ}) using the Reciprocal (RSOR), Product-Over-Sum (R2×R3R2+R3\frac{R_2 \times R_3}{R_2 + R_3}), or Value-Over-Number (RN\frac{R}{N}) method.
Step 2 Redraw the Circuit & Solve for Total Resistance (RTR_T) Redraw the schematic as a simple series circuit with REQR_{EQ} replacing the parallel bank, then add all series resistances together:
RT=R1+REQR_T = R_1 + R_{EQ}
Step 3 Find Total Current (ITI_T) Using total resistance (RTR_T) and applied voltage (VAV_A), calculate total circuit current via Ohm’s Law:
IT=VARTI_T = \frac{V_A}{R_T}
Because R1R_1 and the parallel bank (REQR_{EQ}) are in series with the source, IR1=IREQ=ITI_{R1} = I_{REQ} = I_T.
Step 4 Solve for Series Voltage Drops (VR1,VREQV_{R1}, V_{REQ}) Using common series current (ITI_T), calculate the voltage drop across each series element and across the equivalent parallel bank:
VR1=IT×R1andVREQ=IT×REQV_{R1} = I_T \times R_1 \qquad\text{and}\qquad V_{REQ} = I_T \times R_{EQ}
(Verify with KVL: VA=VR1+VREQV_A = V_{R1} + V_{REQ}.)
Step 5 Solve for Parallel Branch Currents (IR2,IR3I_{R2}, I_{R3}) Expand REQR_{EQ} back into its parallel branches. Because voltage is common in parallel, the voltage across every branch in that bank equals VREQV_{REQ} (VR2=VR3=VREQV_{R2} = V_{R3} = V_{REQ}). Calculate each branch current:
IR2=VREQR2andIR3=VREQR3I_{R2} = \frac{V_{REQ}}{R_2} \qquad\text{and}\qquad I_{R3} = \frac{V_{REQ}}{R_3}
(Verify with KCL: IR2+IR3=ITI_{R2} + I_{R3} = I_T.)
Step 6 Solve for Individual & Total Power (PP) Calculate power for each resistor (Px=Ix×VxP_x = I_x \times V_x) and verify that the sum of all individual resistor powers equals total circuit power:
PT=PR1+PR2+PR3=IT×VAP_T = P_{R1} + P_{R2} + P_{R3} = I_T \times V_A

2. Loaded Voltage Dividers & The 10:1 Rule

When an external device or circuit (Load, RLR_L) is connected to tap a specific voltage off a series voltage divider, RLR_L is wired in parallel with one of the voltage divider’s resistors (R2R_2), transforming the circuit into a series-parallel loaded voltage divider.

Key Loaded Voltage Divider Concepts

  1. The Load (RLR_L): Represents the external component or subsystem being powered by the voltage divider (absorbs power to perform work).
  2. The Loading Effect: Connecting RLR_L in parallel with R2R_2 creates a parallel bank whose equivalent resistance (REQ=R2∥RLR_{EQ} = R_2 \parallel R_L) is always smaller than R2R_2 alone.
    • Because REQR_{EQ} decreases, total circuit resistance (RT=R1+REQR_T = R_1 + R_{EQ}) decreases, total current (ITI_T) increases, the voltage drop across series resistor R1R_1 (VR1=IT×R1V_{R1} = I_T \times R_1) increases, and the output voltage across the load (VLV_L / VoutV_{\text{out}}) DECREASES (“droops”).
    • Proportionality Summary:
      Smaller RL  ⟹  Smaller REQ  ⟹  Smaller Output Voltage (VL)  ⟹  Larger Load Current (IL)\text{Smaller } R_L \implies \text{Smaller } R_{EQ} \implies \text{Smaller Output Voltage } (V_L) \implies \text{Larger Load Current } (I_L)
  3. The 10:1 Loading Rule: To prevent unacceptable output voltage loss when the load is connected, a voltage divider is designed so that the load resistance (RLR_L) is at least 10 times10\text{ times} greater than the bleeder resistor (R2R_2) (RL≥10×R2R_L \ge 10 \times R_2).
    • Example: If R1=2 kΩR_1 = 2,\text{k}\Omega and R2=4 kΩR_2 = 4,\text{k}\Omega, choosing RL≥40 kΩR_L \ge 40,\text{k}\Omega keeps REQR_{EQ} (4 kΩ∥40 kΩ=3.64 kΩ4,\text{k}\Omega \parallel 40,\text{k}\Omega = 3.64,\text{k}\Omega) close to 4 kΩ4,\text{k}\Omega, minimizing voltage droop.
  4. Load Current (ILI_L) vs. Bleeder Current (IR2I_{R2}):
    • Load Current (ILI_L): Current flowing through the load device (RLR_L).
    • Bleeder Current (IR2I_{R2}): Current flowing through the divider resistor (R2R_2) in the branch parallel to the load.

3. Worked Circuit & Fault Demonstrations

Demonstration 1: Complete 6-Step Calculation

Given: VA=15 VV_A = 15,\text{V}, series resistor R1=1 kΩR_1 = 1,\text{k}\Omega, and parallel branches R2=2 kΩ∥R3=3 kΩR_2 = 2,\text{k}\Omega \parallel R_3 = 3,\text{k}\Omega.

Demonstration 2: Faulted Circuit — SHORT in a Parallel Branch (PA #2)

Given: VA=12 VV_A = 12,\text{V}, series R1=470 ΩR_1 = 470,\Omega, R2=SHORTR_2 = \text{SHORT} (0 Ω0,\Omega), R3=2.4 kΩR_3 = 2.4,\text{k}\Omega.

Demonstration 3: Faulted Circuit — OPEN in a Parallel Branch (PA #3)

Given: VA=1.5 VV_A = 1.5,\text{V}, series R1=1 ΩR_1 = 1,\Omega, parallel R2=4 ΩR_2 = 4,\Omega, R3=OPENR_3 = \text{OPEN} (∞ Ω\infty,\Omega).


4. Bench & Troubleshooting Application (BE.01.08 Lab)

In the BE.01.08 breadboard lab, the standard reference circuit across VA=5 VDCV_A = 5,\text{VDC} uses:

Diagnostic Decision Matrix for Series-Parallel Faults

Component Fault Total Resistance (RTR_T) Total Current (ITI_T) Series Drop (VR1V_{R1}) Parallel Bank Voltage (VREQ=VR2=VR3V_{REQ} = V_{R2} = V_{R3}) Key Identifying Signature
R1R_1 (Series) OPEN OL (∞\infty) 0 A0,\text{A} VAV_A (5.0 V5.0,\text{V}) 0.0 V0.0,\text{V} Full source voltage across R1R_1; 0 V0,\text{V} across parallel bank.
R1R_1 (Series) SHORTED REQR_{EQ} (830 Ω830,\Omega) ↓\downarrow Increases (↑\uparrow) 0.0 V0.0,\text{V} VAV_A (5.0 V5.0,\text{V}) ↑\uparrow 0 V0,\text{V} across R1R_1; full source voltage appears across the parallel bank.
R2R_2 or R3R_3 (Parallel) OPEN Increases (↑\uparrow) (R1+RintactR_1 + R_{\text{intact}}) Decreases (↓\downarrow) Decreases (↓\downarrow) Increases (↑\uparrow) Lower ITI_T causes R1R_1 to drop less voltage, so by KVL (VREQ=VA−VR1↓V_{REQ} = V_A - V_{R1}\downarrow), parallel bank voltage increases!
R2R_2 or R3R_3 (Parallel) SHORTED R1R_1 (330 Ω330,\Omega) ↓\downarrow Increases (↑\uparrow max) VAV_A (5.0 V5.0,\text{V}) ↑\uparrow 0.0 V0.0,\text{V} Shorted branch zeroes out REQR_{EQ} and VREQV_{REQ}; R1R_1 drops 100%100% of VAV_A.
R2R_2 or R3R_3 Value INCREASED Increases (↑\uparrow) Decreases (↓\downarrow) Decreases (↓\downarrow) Increases (↑\uparrow) Measure isolated branch resistances with power off to pinpoint which resistor drifted high.
R2R_2 or R3R_3 Value DECREASED Decreases (↓\downarrow) Increases (↑\uparrow) Increases (↑\uparrow) Decreases (↓\downarrow) Lower REQR_{EQ} pulls VREQV_{REQ} down and drives VR1V_{R1} up.

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